1.27.8 AHB Bus Matrix (MATRIX)

In order to reduce power consumption without loss in performance, the system embeds three matrixes: one based on the AXI protocol (AXIMX) and two based on the AHB protocol (H64MX and H32MX).

This section describes the implementation of the 64-bit AHB Matrix (H64MX) and the 32-bit AHB Matrix (H32MX). Each AHB Matrix implements a multilayer AHB, based on the AHB-Lite protocol, which enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth.

The normal latency to connect a master to a slave is one cycle, except for the default master of the accessed slave which is connected directly (zero cycle latency).

Using The Library

Matrix initializes AHB Masters and Slaves by invoking Matrix_Initialize() function in the system initialization.

Library Interface

AHB Bus Matrix peripheral library provides the following interfaces:

Functions

Name	Description
MATRIX_Initialize	Initialize AHB Masters and Slaves