1.27.10 1.28.11 ARM MMU V7A

The MMU works with the L1 and L2 memory system to translate virtual addresses to physical addresses. It also controls accesses to and from external memory. The ARM v7 Virtual Memory System Architecture (VMSA) features include the following:

• Page table entries that support:

  • 16 Mbyte supersections. The processor supports supersections that consist of 16 Mbyte blocks of memory.

  • 1 Mbyte sections

  • 64 Kbyte large pages

  • 4 Kbyte small pages

  • 16 access domains

• Global and application-specific identifiers to remove the requirement for context switch TLB flushes.

• Extended permissions checking capability.

TLB maintenance and configuration operations are controlled through a dedicated coprocessor, CP15, integrated with the core. This coprocessor provides a standard mechanism for configuring the L1 memory system.

Using The Library

This Plib Initializes MMU with a flat address map (e.g. physical and virtual addresses are the same) and enable MMU and caches by invoking MMU_Initialize() in the system initialization.

Library Interface

ARM MMU V7A peripheral library provides the following interfaces:

Functions

Name	Description
MMU_Initialize	Initialize and enable MMU
icache_InvalidateAll	Invalidate instruction cache
icache_Enable	Enable instruction cache
icache_Disable	Disable instruction cache
dcache_InvalidateAll	Invalidate Data Cache
dcache_CleanAll	Clean Data Cache
dcache_CleanInvalidateAll	Clean and Invalidate Data Cache
dcache_InvalidateByAddr	Invalidate Data Cache by address
dcache_CleanByAddr	Clean Data Cache by address
dcache_CleanInvalidateByAddr	Clean Data Cache by address
dcache_Enable	Enable data cache
dcache_Disable	Disable data cache