1.26.6.44 1.27.9.44 1.28.10.44 1.34.7.44 1.41.8.44 1.42.6.44 MCAN_ERROR_DLEC_BIT0 Macro

C

#define MCAN_ERROR_DLEC_BIT0 0x500U

Summary

MCAN Error DLEC_BIT0

Description

Data Phase - During transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device tried to send a dominant level (data or identifier bit logical value ‘0’), but the monitored bus value was recessive. During Bus_Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).

Remarks

None.