1.26.3 Clock Generator (CLOCK)

The Clock system generates and distributes the clock for the processor and peripherals

Clock Generators:

  • A low-power 32.768 kHz oscillator supporting crystals, resonators and Bypass mode

  • An embedded always-on, slow RC oscillator generating a typical 32 kHz clock

  • A 20 to 50 MHz oscillator supporting crystals, resonators and Bypass mode

  • A main RC oscillator generating a typical 12 MHz c

  • Five fractional-N PLLs with an input range of 20 to 50 MHz and different internal frequency ranges : System PLL (PLLA), USB High-speed PLL (UPLL), Audio PLL (AUDIOPLL), LVDS PLL (LVDSPLL), System PLL divided by 2 (PLLADIV2)

Clock Distribution:

  • MD_SLCK-Monitoring Domain Slow clock. This clock, sourced from the always-on Slow RC oscillator only, is the only permanent clock of the system and feeds safety-critical functions of the device (WDT, RSTC, SCKC, frequency monitors and detectors, PMC startup time counters).

  • TD_SLCK-Timing Domain Slow clock. This clock, sourced from the 32.768 kHz crystal oscillator or the always-on Slow RC oscillator, is routed to the RTC and RTT peripherals.

  • MAINCK-Output of the Main clock oscillator selection. This clock is either the Main crystal oscillator or Main RC oscillator.

  • PLL Clocks-Outputs of embedded PLLs

  • Main System Bus Clock (MCK)-programmable from a few hundred Hz to the maximum operating frequency of the device. It is available to the modules running permanently.

  • Processor Clock (CPU_CLK)-can be tuned through a frequency scaler module and automatically switched off when entering the processor in Sleep mode.

  • Free-running Processor Clock (FCLK)-the source clock of CPU_CLK. Is not affected when Sleep mode is activated.

  • UHDP Clocks (UHP48M and UHP12M)-required by USB Host Device Port operations.

  • Peripheral Clocks with independent ON/OFF control, provided to the peripherals. Each peripheral clock is inherited from MCK.

  • Programmable Clock Outputs (PCKx), selected from the clock generator outputs to drive the device PCKx pins.

  • Generic Clock (GCLK) with controllable division and ON/OFF control, independent of MCK and CPU_CLK. Provided to selected peripherals.

Using The Library

The Clock peripheral library initializes the clock system as configured by the user in the MHC Clock configurator. It can be accessed via the "Tools" drop down of the MPLAB harmony configurator menu bar.

Library Interface

Clock Generator peripheral library provides the following interfaces:

Functions

Name Description
CLK_Initialize Initializes hardware of the System Clock and Peripheral Clock