1.2.19.20 1.3.22.20 1.4.20.20 1.5.21.20 1.6.21.20 1.7.22.20 1.29.21.20 1.30.15.15 1.31.15.15 1.32.24.20 1.33.15.15 1.37.15.15 1.38.20.20 1.39.17.20 1.40.19.20 RTC_TIMER32_INT_MASK Enum

C

/* Enum members will vary based on the device used, please refer the plib header file */

typedef enum
{
    /* Compare0 match interrupt */
    RTC_TIMER32_INT_MASK_CMP0,
    
    /* Compare1 match interrupt */
    RTC_TIMER32_INT_MASK_CMP1,
    
    /* Counter Overflow interrupt */
    RTC_TIMER32_INT_MASK_OVF,
    
    /* Peridic Interrupt - Prescaler Bit 0 */
    RTC_TIMER32_INT_MASK_PER0,
    
    /* Peridic Interrupt - Prescaler Bit 1 */
    RTC_TIMER32_INT_MASK_PER1,
    
    /* Peridic Interrupt - Prescaler Bit 2 */
    RTC_TIMER32_INT_MASK_PER2,
    
    /* Peridic Interrupt - Prescaler Bit 3 */
    RTC_TIMER32_INT_MASK_PER3,
    
    /* Peridic Interrupt - Prescaler Bit 4 */
    RTC_TIMER32_INT_MASK_PER4,
    
    /* Peridic Interrupt - Prescaler Bit 5 */
    RTC_TIMER32_INT_MASK_PER5,
    
    /* Peridic Interrupt - Prescaler Bit 6 */
    RTC_TIMER32_INT_MASK_PER6,
    
    /* Peridic Interrupt - Prescaler Bit 7 */
    RTC_TIMER32_INT_MASK_PER7,
    
    /* Tamper Detection*/
    RTC_TIMER32_INT_MASK_TAMPER
    
} RTC_TIMER32_INT_MASK;

// OR

typedef enum
{
    /* Compare match interrupt */
    RTC_TIMER32_INT_MASK_COMPARE_MATCH,
    
    /* Counter Overflow interrupt */
    RTC_TIMER32_INT_MASK_COUNTER_OVERFLOW,
} RTC_TIMER32_INT_MASK;

Summary

Possible RTC 32-bit Timer Counter Mode Events.

Description

This enumeration defines the possible events that can occur when the RTC peripheral is configured for 32-bit Timer Counter mode operation. These events are passed into the callback function registered through the RTC_Timer32CallbackRegister() function.

Remarks

Enum members will vary based on device being used. Refer to the device datasheet.